A 2.5V 10b 120 Msample/s CMOS pipelined ADC with high SFDR - Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
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چکیده
A 10b multibit-per-stage pipelined ADC incorporating merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are f0.40 LSB and f0.48 LSB, respectively. The ADC fabricated in a 0.25 pm CMOS occupies 3.6 mm2 active die area and consumes 208 mW under a 2.5V power supply. 0 .MO * A ISSCC 1997 (9) Proposed ADC
منابع مشابه
A 2.5V 10b 120 MSample/s CMOS Pipelined ADC with high SFDR
A 10b multibit-per-stage pipelined ADC incorporating merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are ±0.40 LSB and ±0.48 LSB, respectively. The ADC fabricated in a 0.25 μm CMOS occupies 3.6 mm active die area and consumes 208 mW under a 2.5...
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